The present invention relates generally to program counters and, more specfically, to an integrated structure for a program counter, a memory storage device and an incrementer system for the program counter.
In the architecture of a computer, a circuit called the program counter (PC) must be included. The program counter keeps track of the next instruction to be executed and must be incremented for each access and, also, must have the capability of being written into for special jump locations. In some designs, the program counter is a location in memory or in others there is a requirement that it be part of general register array. When the program counter is part of the memory array, the contents are read, incremented external to the array and then rewritten back into the memory. Where the program counter is part of a register array, the program counter must be connected so that it can be read from and into, like any other register, and still have the capability of being incremented. In either situation, a ALU must be used.
Another important element of the computer architecture is a memory management register (MMR) which is periodically updated with the contents of the program counter. This is used to store the address of the present instruction being operated upon such that if an interrupt or any other type of jump operation should occur, the address of the instruction at such interrupt may be retained since the program counter has already been incremented and includes the next instruction address. Thus, the memory management register must be capable of being read from as well as having the contents of the program counter written therein. As with the program counter, the memory management register generally is a register versus a location in memory.
In prior art designs, wherein the program counter is part of the general register array, the A and B buses of the array as well as the arithmetic logic unit (ALU) must be available to read and write into and out of the program counter and the memory management register as well as to increment the program counter. In certain designs, the A and B buses and the ALU are not available without providing a special cycle. This decreases the speed of operation of the computer and is, therefore, undesirable. Thus, there exists the need for a new architecture of a program counter and memory management register which is part of the register array which does not require any of the cycle time for the A and B bus as well as the ALU to perform the necessary writing of the program counter into the memory management register as well as incrementing the program counter.